5、NAND FLASH ACCESS
6410 does not support NAND flash access mechanism directly. It only supports signal control mechanism for NAND flash access. Therefore software is responsible for accessing NAND flash memory correctly.
S3C6410 仅支持软件模式访问。
1. Writing to the command register (NFCMMD) = the NAND Flash Memory command cycle
2. Writing to the address register (NFADDR) = the NAND Flash Memory address cycle
3. Writing to the data register (NFDATA) = write data to the NAND Flash Memory (write cycle)
4. Reading from the data register (NFDATA) = read data from the NAND Flash Memory (read cycle)
5. Reading main ECC registers and Spare ECC registers (NFMECCD0/1, NFSECCD) = read data from the
NAND Flash Memory
In NAND flash access, you must check the RnB status input pin by polling the signal or using interrupt.
（1）写命令寄存器=NAND FLASH 存储器命令周期。
（2）写地址寄存器=NAND FLASH 存储器地址周期。
（3）写数据寄存器=写数据到NAND FLASH 存储器（写周期）。
（4）读数据寄存器=从NAND FLASH 存储器读数据（读周期）。
（5）读主ECC 寄存器和备用ECC 寄存器=从NAND FLASH 存储器读数据。
在软件模式下，必须通过利用检测和中断来检查RnB 输入引脚的状态。
6、1-BIT / 4-BIT / 8-BIT ECC (ERROR CORRECTION CODE)
NAND flash controller has four ECC (Error Correction Code) modules for 1 bit ECC , one for 4bit ECC and one for
8bit ECC. NAND FLASH 控制器有4 个ECC（错误纠正码）模块用于SLC 类型的NAND FLASH 存储器，1 个ECC 模块用于MLC 类型的NAND FLASH 存储器。
The 1bit ECC modules for main data area can be used for (up to) 2048 bytes ECC parity code generation, and 1
bit ECC module for spare area can be used for (up to) 4 bytes ECC Parity code generation.这些模块对于主存储区可用于（高达）2048 字节ECC 奇偶校验码的产生，对于备用区可用于（高达）4 字节ECC 奇偶校验码的产生。
Both 4bit and 8bit ECC modules can be used for only 512 bytes ECC parity code generation.
4 bit and 8bit ECC modules generate the parity codes for each 512 byte. However, 1 bit ECC modules generate
parity code per byte lane separately.
6.1、ECC MODULE FEATURES
ECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit of the Control register. When
ECCLock is Low, ECC codes are generated by the H/W ECC modules
4bit ECC modules generate max 7byte parity codes and 8 bit ECC modules generate 13byte parity codes at each
512/24 bytes.
ECC 的产生是通过ECC 锁定（MainECCLock，SpareECCLock）位的控制寄存器来控制的。当ECCLock 为低时，ECC 校验码通过H/W ECC 模块产生。